Core

• 32-bit Arm^® Cortex^®-M0+ processor core
• Up to 20 MHz operating frequency
• Single-cycle multiplication
• Integrated Nested Vectored Interrupt Controller (NVIC)
• 24-bit SysTick timer

On-chip Memory

• 64 KB on-chip Flash memory for instruction/data and option byte storage
• 8 KB on-chip SRAM
• Supports multiple boot modes

Flash Memory Controller – FMC

• 32-bit word programming with In System Programming (ISP) and In Application Programming (IAP)
• Flash protection capability to prevent illegal access

Reset Control Unit – RSTCU

• Supply supervisor
  - Power On Reset / Power Down Reset – POR/PDR
  - Brown-out Detector – BOD
  - Programmable Low Voltage Detector – LVD

Clock Control Unit – CKCU

• External 4 to 20 MHz crystal oscillator
• External 32.768 kHz crystal oscillator
• Internal 20 MHz RC oscillator trimmed to ±2 % accuracy at 25 °C operating temperature
• Internal 32 kHz RC oscillator
• Independent clock divider and gating bits for peripheral clock sources

Power Management – PWRCU

• Flexible power supply: V_DD power supply (2.5 V ~ 5.5 V), V_DDIO for I/Os (1.8 V ~ 5.5 V)
• Integrated 1.5 V LDO regulator for MCU core, peripherals and memories power supply
• V_DD, V_DDIO and V_CORE power domains
• Three power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2

Power Delivery

• Compliant with USB PD 3.1/PPS specification
• Supports Dual Role Port – DRP
• Supports Fast Role Swap – FRS
• Integrated VCONN Switch
• Integrated HVO switch output

Real Time Clock – RTC

• 24-bit up-counter with a programmable prescaler
• Alarm function
• Interrupt and Wake-up event

External Interrupt/Event Controller – EXTI

• Up to 16 EXTI lines with configurable trigger source and type
• All GPIO pins can be selected as EXTI trigger source
• Source trigger type includes high level, low level, negative edge, positive edge or both edges
• Individual interrupt enable, wakeup enable and status bits for each EXTI line
• Software interrupt trigger mode for each EXTI line
• Integrated deglitch filter for short pulse blocking

Hardware Divider – DIV

• Signed/unsigned 32-bit divider
• Operation in 8 clock cycles, load in 1 clock cycle
• Division by zero error Flag

Analog to Digital Converter – ADC

• 12-bit SAR ADC engine
• Up to 1 Msps conversion rate
• Up to 9 external analog input channels

I/O Ports – GPIO

• Up to 28 GPIOs
• Port A, B, C are mapped as 16 external interrupts – EXTI
• Almost all I/O pins have configurable output driving current

Basic Function Timer – BFTM

• 32-bit compare match count-up counter – no I/O control
• One shot mode – counter stops counting when compare match occurs
• Repetitive mode – counter restarts when compare match occurs

Motor Control Timer – MCTM

• 16-bit up, down, up/down auto-reload counter
• Up to 4 independent channels
• 16-bit programmable prescaler that allows division of the prescaler clock source by any factor between 1 and 65536 to generate the counter clock frequency
• Input Capture function
• Compare Match Output
• PWM waveform generation with Edge-aligned and Center-aligned Counting
• Single Pulse Mode Output
• Complementary Outputs with programmable dead-time insertion
• Break input to force the timer’s output signals into a reset or fixed condition

General-Purpose Timer – GPTM

• 16-bit up, down, up/down auto-reload counter
• Up to 4 independent channels
• 16-bit programmable prescaler that allows division of the prescaler clock source by any factor
  between 1 and 65536 to generate the counter clock frequency
• Input Capture function
• Compare Match Output
• PWM waveform generation with Edge-aligned and Center-aligned Counting
• Single Pulse Mode Output
• Encoder interface controller with two inputs using quadrature decoder

Pulse-Width-Modulation Timer – PWM

• 16-bit up, down, up/down auto-reload counter
• Up to 4 independent channels for each timer
• 16-bit programmable prescaler that allows division of the prescaler clock source by any factor between 1 and 65536 to generate the counter clock frequency
• Compare Match Output
• PWM waveform generation with Edge-aligned and Center-aligned Counting
• Single Pulse Mode Output

Watchdog Timer – WDT

• 12-bit down counter with 3-bit prescaler
• Provides reset to the system
• Programmable watchdog timer window function
• Register write protection function

Inter-integrated Circuit – I²C

• Supports both master and slave modes with a frequency of up to 1 MHz
• Provides an arbitration function and clock synchronization
• Supports 7-bit and 10-bit addressing modes and general call addressing
• Supports slave multi-addressing mode with address mask function

Serial Peripheral Interface – SPI

• Supports both master and slave modes
• Frequency of up to (f_PCLK/2) MHz for the master mode and (f_PCLK/3) MHz for the slave mode
• FIFO Depth: 8 levels
• Multi-master and multi-slave operation

Universal Synchronous Asynchronous Receiver Transmitter –
USART

• Supports both asynchronous and clocked synchronous serial communication modes
• Programmable baud rate clock frequency up to (f_PCLK/16) MHz for Asynchronous mode and (f_PCLK/8) MHz for synchronous mode
• Full duplex communication
• Fully programmable serial communication characteristics including:
  - Word length: 7, 8 or 9-bit character
  - Parity: Even, odd or no-parity bit generation and detection
  - Stop bit: 1 or 2 stop bits generation
  - Bit order: LSB-first or MSB-first transfer
• Error detection: Parity, overrun and frame error
• Auto hardware flow control mode – RTS, CTS
• IrDA SIR encoder and decoder
• RS485 mode with output enable control
• FIFO Depth: 8-level for both receiver and transmitter

Universal Asynchronous Receiver Transmitter – UART

• Asynchronous serial communication operating baud-rate clock frequency up to (f_PCLK/16) MHz
• Full duplex communication
• Fully programmable serial communication characteristics including:
  - Word length: 7, 8 or 9-bit character
  - Parity: Even, odd or no-parity bit generation and detection
  - Stop bit: 1 or 2 stop bits generation
  - Bit order: LSB-first or MSB-first transfer
• Error detection: Parity, overrun and frame error

Cyclic Redundancy Check – CRC

• Supports CRC16 polynomial: 0x8005,
  X¹⁶+X¹⁵+X²+1
• Supports CCITT CRC16 polynomial: 0x1021,
  X¹⁶+X¹²+X⁵+1
• Supports IEEE-802.3 CRC32 polynomial: 0x04C11DB7, X³²+X²⁶+X²³+X²²+X¹⁶+X¹²+X¹¹+X¹⁰+X⁸+X⁷+X⁵+X⁴+X²+X+1
• Supports 1’s complement, byte reverse & bit reverse operation on data and checksum
• Supports byte, half-word & word data size
• Programmable CRC initial seed value
• CRC computation executed in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for 32-bit data

Debug Support

• Serial Wire Debug Port – SW-DP
• 4 comparators for hardware breakpoint or code / literal patch
• 2 comparators for hardware watch points

Package and Operation Temperature

• 46-pin QFN package
• Operation temperature range: -40 °C to 85 °C